In Very-Large-Scale Integration (VLSI) chip design, there is often a need to delay a signal. This is typically accomplished by introducing delay elements, such as logic gates or wires, along a signal path, where a linear delay line having N delay elements achieves a delay of O(N). However, the more delay elements that are required, the more area that is needed, which increases routing congestion and the chances that cross-coupling and noise issues will arise.